Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.

Position Summary

The Staff ECAD Engineer is the technical lead for PCB design and fabrication across all high performance RF and power product lines, combining master level CAD/layout expertise with deep IPC knowledge. This individual contributor role sets standards and design rules, resolves the most complex signal integrity, power integrity, and reliability challenges, and drives quality improvements across programs. The role leads through influence, mentoring Staff and Senior engineers and setting technical direction.

Key Responsibilities

• Independently execute end-to-end PCB design using Altium or Cadence tools, including schematic capture and complex PCB layout, from concept to fabrication, assembly, and production builds.
• Set standards, design rules, and IPC compliance practices. Provide sign-off on complex, high frequency PCB designs and fabrication documentation (Altium, Cadence Allegro, ADS, SolidWorks, AutoCAD).
• Lead root cause investigation and corrective action for design/fabrication issues involving IPC standards, signal integrity, thermal, and mechanical interactions.
• Provide expert DFM/stack-up guidance from concept through NPI, partnering with RF, Mechanical, Component, and Process Engineering.
• Mentor Staff and Senior engineers as a technical resource and design reviewer across programs.
• Perform pre and post layout SI/PI/EM analysis (Cadence Sigrity or equivalent tools) to validate high speed and high frequency designs.
• Develop transmission line models, impedance controlled routing, crosstalk, and PDN analysis; drive simulation based optimization for DDR4/DDR5, PCIe, SerDes, Ethernet, USB, and RF interfaces.
• Present simulation findings and risk mitigation recommendations at design reviews.
• Apply HDI techniques for high pin count, fine pitch BGA routing on complex multilayer boards.
• Apply DFx methodologies (DFM, DFA, DFT, DFR) to ensure manufacturability, testability, and reliability.
• Partner with Hardware, Mechanical, Procurement, Manufacturing, and Program Management to align designs with product requirements and schedules.
• Work with suppliers to improve process capability, yield, cycle time, cost, and support qualification and audits of RF/high frequency fabrication partners.
• Prepare and manage complete design documentation packages, including fabrication and assembly drawings, Gerber files, BOMs, and Engineering Change Orders (ECOs), ensuring accuracy and traceability with timely release and smooth transition into manufacturing, while collaborating closely with cross functional stakeholders.
• Manage the lifecycle of Technical Queries (TQs), ensuring timely resolution and clear communication.

Required Qualifications

• Bachelor's degree in Electrical Engineering, Electronic Engineering, Materials Science, or related field; equivalent extensive practical experience considered in lieu of degree.
• 15+ years of combined experience in PCB/PWB design, CAD layout, and/or fabrication/supplier development, with demonstrated progression into a senior technical role. IPC certification(s) required.
• Deep proficiency with ECAD/mechanical CAD tools: Altium, Cadence Allegro, ADS, AutoCAD, SolidWorks, and CAM350.
• Extensive hands on knowledge of PCB/PWB manufacturing processes, materials, and IPC standards, with proven application of GD&T and DFM/DFA/DFT/DFR principles.
• Strong RF/high frequency design background, including high frequency laminates (Rogers, PTFE/Teflon) and demanding applications such as ATE multisite load boards and probe cards.
• Hands on experience with Cadence Sigrity or equivalent program and related SI/PI/EM simulation environments.
• Strong understanding of transmission line theory, impedance control, signal propagation, reflection, crosstalk, termination methods, PDN, and grounding.
• Experience with pre and post layout SI/PI analysis for DDR4/DDR5, PCIe, Ethernet, USB, SerDes, and high-speed ATE applications.
• Excellent written/verbal communication skills, including presenting technical findings to cross functional audiences.
• Proficiency with Microsoft Office and engineering documentation/PLM systems.
• Ability to independently manage competing priorities across multiple concurrent programs.

This position is not eligible for visa sponsorship by the Company.

Competitive base salary commensurate with experience: $125,400 - $163,000 (subject to change dependent on physical location) 

Posted salary ranges are made in good faith. Qorvo reserves the right to adjust ranges depending on the experience/qualification of the selected candidate as well as external competitiveness and internal comparability. 

Base compensation is one element of Total Rewards offered at Qorvo. More information on the Total Rewards package can be shared upon request. 

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MAKE A DIFFERENCE AT QORVO   

 We are Qorvo. We do more than create innovative RF and Power solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.

We are an Equal Employment Opportunity (EEO) employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to any characteristics protected by applicable law, including race, color, religion, sex (as defined by law), national origin, age, military or veteran status, genetic information, or disability.