Layout Engineer

The IC Layout Engineer is responsible for converting an electrical design to a mask layout used for chip fabrication. He/She is responsible for the physical representation of the chip, from the lowest block level to the complete floor plan. This will be done in close collaboration with the circuit designers and project leaders.

RESPONSIBILITIES:

• Work as a team player in the Layout IC Design team.
• Work with engineers in local and international design teams on innovative standard cell and pixel layouts with the most advanced CIS technologies.
• Responsibilities include all aspects of IC mask design from creating block layouts to the completed floor plans; planning schedules, hookup, and verification to tape-out.
• Demonstrates a clear, discipline-specific understanding of the design process.
• Organize to review and work with the circuit designers and peers
• Successfully execute responsibilities in adherence to Qorvo’s engineering process.

QUALIFICATIONS:

• Bachelor's Degree in Electrical, Electronic, and Telecommunication.
• At least 2 years of proven experience in the equivalent position and project management.
• Eager and quick to learn in Layout design, verification and work with SoC teams.
• Read and understand detailed material specifications and make design / layout decisions on these specifications.
• Understanding the physical reason being Design Rule Checks, Layout versus Schematics verification and other physical and electrical design rules will be essential
• Have excellent teamwork skill
• Below are the qualifications that are preferred:
  • Good English communication skills in speaking and writing. Having presentation skill in English is a plus
  • A good understanding of Analog/Mixed signal CMOS circuit design concepts is an advantage
  • Cadence tools (Virtuoso, LVS/DRC/QRC verification), and Unix is desirable