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Staff Digital Design Engineer

Experience Level:  Individual Contributor
Job Type:  Full-Time
Location: 

NC - Greensboro (HQ), US

Requisition ID:  706

SUMMARY:

Qorvo is seeking a Staff Digital Design Engineer responsible for a wide variety of Digital ASIC Design tasks, which include designing block-level self-checking test benches using modern verification techniques. Designs primarily interface to Analog RF functions, including development of Serial Interfaces, Register Blocks, OTP Blocks, supporting Clock and Reset analog circuits, and timed enabling/switching of Analog signal paths. This position involves the full Digital Design flow including interacting with Systems for Specification generation, Architecture development, RTL description using Verilog/System Verilog, Verilog Simulation Verification via developed Test Benches, Logic Synthesis and associated Static Timing Analysis, executing a Place & Route tool, and familiarization with Scan testing.  Documentation and presentation at Design Reviews is required.

 

RESPONSIBILITIES:

  • Receive Specifications from Module Architects / System Engineers – review, assess, provide feedback, and develop a digital micro-architecture
  • Create Cadence schematic database of Digital Blocks via Virtuoso
  • Generate RTL to comply with specifications, both by manual development and automated generation
  • System Verilog Verification Simulations of the design by creating Test Benches at block level
  • Create new Verification tests and utilize existing tests that are to be modified as needed. Execute both RTL and Gate Simulations
  • Execute Logic Synthesis and Static Timing Analysis
  • Execute remaining back-end tools – Place & Route, LEC, LINT, CDC

 

 QUALIFICATIONS:

  • BSEE required, MSEE preferred
  • 8+ years minimum of relevant experience
  • Experience:
    • System Verilog / Verilog Language and Simulation
    • Scripting languages (TCL, PERL, Python, C/C++, UNIX/LINUX, shell)
    • Synthesis and Static Timing Analysis
  • Preferred Experience:
    • Place & Route using Cadence Virtuoso, verifying Database vs Schematics
    • System Verilog Assertions and Functional Coverage
    • Formal Verification
    • MIPI RFFE Standard, Protocol, and Operation
  • Strong communication skills to interface with other teams

 

#LI-LR1

 

MAKE A DIFFERENCE AT QORVO   

 

We are Qorvo. We do more than create innovative RF solutions for the mobile, defense and infrastructure markets – we are a place to innovate and shape the future of wireless communications. It starts with our employees. As a unified global team, we bring a commitment to excellence, growth and a passion for creating what's next. Explore the possibilities with us.

 

We are an Equal Employment Opportunity (EEO) / Affirmative Action employer and welcome all qualified applicants. Applicants will receive fair and impartial consideration without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, military or veteran status, physical or mental disability, genetic information, and/or any other status protected by law.

Qorvo is an E-Verify Employer. For more information, please see the Right to Work and E-Verify Participation posters.


Nearest Major Market: Greensboro

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