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Design Verification Engineering, Internship

Experience Level:  Internship
Job Type:  Intern

NC - Greensboro (HQ), US

Requisition ID:  3176


Qorvo is seeking an Intern Design Verification Engineer responsible for a wide variety of advanced verification tasks, including designing self-checking test benches using modern verification techniques; designing verification components such as bus functional models, monitors, and behavioral models; implementing functional coverage and assertions; and developing test and functional coverage plans based on device specifications. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing functional coverage results.



  • Participate in the development and improvement of design verification processes and procedures
  • Collaborate with design and systems engineers to architect, define, and specify verification solutions
  • Verification simulations per defined product functionalities and specifications
  • Characterize, verify, and debug digital and analog behavioral functions as needed
  • Understand and reinforce design review, best practice, and other product design processes
  • Deliver documentation of verification test plans and results



  • Capable of Digital RTL Circuit Design, Verification, Synthesis, Place and Route, Timing Closure
  • Scripting language proficiency (Python preferred, C/C++, UNIX/LINUX, PERL, TCL a plus)
  • Hardware Description Language (HDL) proficiency (SystemVerilog preferred)
  • Awareness of Analog Circuit Design Fundamentals to support Verilog Behavioral Modeling
  • Awareness of Circuit Design EDA Tools (e.g. Cadence, Synopsys, Mentor)
  • BSEE required
  • Strong communication skills to interface cross functional teams (design, characterization, test)
  • Professional work experience preferred



Qorvo is an E-Verify Employer. For more information, please see the Right to Work and E-Verify Participation posters.

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